Sandeep Manchella
2011-04-21 19:42:02 UTC
Hello,
I would like to report on the status of the qualification task. The code is
attached.
I finished the code and I am still checking the functionality(I got *some
warnings* due to latch development which result in timing delay and wrong
output also sometimes, so trying to fix those) .I based* my
implementation*on the blowfish vhdl code you mentioned in the mailing
list. I obviously
used the same method for init state, P array and S boxes. The control logic
takes care of the expand-key function and encryption in ECB mode as
different states based on simple muxes.
As of now I am trying to make the code free of warnings so that it can be
properly synthesized without any timing delays. If I can complete this in
the next few hours I will post it on www.openwall.com/john/FPGA or mail you
with the screenshots.
Thanking You,
Sandeep.M
P.S : It took me time to understand the blowfish implementation as I newly
learnt vhdl (around 25 days back) and I did my best :) .
I would like to report on the status of the qualification task. The code is
attached.
I finished the code and I am still checking the functionality(I got *some
warnings* due to latch development which result in timing delay and wrong
output also sometimes, so trying to fix those) .I based* my
implementation*on the blowfish vhdl code you mentioned in the mailing
list. I obviously
used the same method for init state, P array and S boxes. The control logic
takes care of the expand-key function and encryption in ECB mode as
different states based on simple muxes.
As of now I am trying to make the code free of warnings so that it can be
properly synthesized without any timing delays. If I can complete this in
the next few hours I will post it on www.openwall.com/john/FPGA or mail you
with the screenshots.
Thanking You,
Sandeep.M
P.S : It took me time to understand the blowfish implementation as I newly
learnt vhdl (around 25 days back) and I did my best :) .